1. Field of the Invention
The present invention relates to a semiconductor manufacturing method. More specifically, the present invention relates to a method for manufacturing a metal oxide semiconductor (MOS) transistor in a semiconductor device.
2. Description of the Related Art
A conventional MOS transistor manufacturing method comprises: forming isolation layers in a semiconductor substrate; forming a gate oxide layer and a poly-silicon layer on the substrate; patterning the gate oxide layer and the poly-silicon layer to form a gate electrode; and implanting impurities in the substrate beside the gate electrode to form source and drain regions.
According to the trend of high-integration and low source power in semiconductor devices, the dimension and the driving voltage of the MOS transistor are decreasing more and more. Recently, semiconductor devices operated under at least two different-valued driving sources in one chip have been developed. For example, a semiconductor chip in use of a cellular phone includes a low-voltage MOS transistor operated under a relatively low driving voltage of about 1.2V, and a high-voltage MOS transistor operated under a relatively high driving voltage of about 3.3V.
FIGS. 1a to 1e are cross-sectional views illustrating a method for manufacturing MOS transistors in a semiconductor substrate, according to a conventional art. Referring to these drawings, a method for manufacturing a semiconductor device including a low-voltage MOS transistor and a high-voltage MOS transistor will be explained in detail. Here, reference symbols A and B indicate a region for a low-voltage MOS transistor, and a region for a high-voltage MOS transistor, respectively.
As shown in FIG. 1a, isolation layers 12 are formed in a semiconductor substrate 10, e.g., a silicon substrate, according to a shallow trench isolation (STI) process. Then, a photoresist pattern 14 is formed on the semiconductor substrate 10 including the isolation layers 12, using a photolithography process, to expose the low-voltage MOS transistor region A. Using a well implantation process, conductive impurities are implanted in the substrate 10 of the low-voltage MOS transistor region A to form a first well 16. For example, in the case of a N-channel MOS (NMOS) transistor, the well implantation is performed under conditions comprising boron (B) ions as a first conductivity type of impurity (i.e., P-type impurity), an implantation energy of 260 KeV, and a dose of 2E13 ions/cm2. Alternatively, in the case of a P-channel MOS (PMOS) transistor, the well implantation is performed under conditions comprising phosphorus (P) ions as a second conductivity type of impurity (i.e., N-type impurity), an implantation energy of 500 KeV, and a dose of 1E13 ions/cm2, or comprising arsenic (As) ions as a second conductivity type of impurity, an implantation energy of 100 KeV, and a dose of 3.5E12 ions/cm2. After then, the photoresist pattern 14 is removed using an ashing process.
As shown in FIG. 1b, a photoresist pattern 18 is formed, using a photolithography process, to expose the high-voltage MOS transistor region B. Using a well implantation process, conductive impurities are implanted in the substrate 10 of the high-voltage MOS transistor region B to form a second well 20. For example, in the case of a NMOS transistor, the second well implantation is preferably performed under conditions comprising boron (B) ions as a first conductivity type of impurity, an implantation energy of 260 KeV, and a dose of 2E13 ions/cm2. Similarly, in the case of a PMOS transistor, the second well implantation is preferably performed under conditions comprising phosphorus (P) ions as a second conductivity type of impurity, an implantation energy of 500 KeV, and a dose of 1E13 ions/cm2. After then, the photoresist pattern 18 is removed using an ashing process.
Subsequently, as shown in FIG. 1c, the semiconductor substrate 10, comprising the first well 16 and the second well 20, undergoes a thermal oxidation process, thus a gate oxide layer is formed thereon. Then, a doped poly-silicon layer is deposited on the gate oxide layer. The doped poly-silicon layer and the gate oxide layer are patterned by a dry etching process using a gate mask, thus forming gate electrodes 24 and gate oxide layer patterns 22 on the first and second wells 16 and 20, respectively.
Next, as shown in FIG. 1d, a photoresist pattern 26 is formed on the semiconductor substrate 10 to expose the low-voltage MOS transistor region A. Using an implantation process for a lightly doped drain (LDD) structure, impurities are implanted in the substrate 10 exposed by the gate electrode 24 in the low-voltage MOS transistor region A, thus forming a first LDD region 28. Here, the conductivity type of the LDD structure is opposite to the conductivity type of the well region. For example, in the first LDD implantation for a NMOS transistor, B or BF2 ions as a first conductivity type of impurity are implanted under conditions comprising an implantation energy of 50 KeV and a dose of about 2.3E13 ions/cm2, and continuously As ions as a second conductivity type of impurity are implanted under conditions comprising an implantation energy of 3 KeV and a dose of 9.6E14 ions/cm2. In the first LDD implantation for a PMOS transistor, As ions as a second conductivity type of impurity are implanted under conditions comprising an implantation energy of 60 KeV and a dose of 2.7E13 ions/cm2, and continuously B ions as a first conductivity type of impurity are implanted under conditions comprising an implantation energy of 2.5 KeV and a dose of 5.2E14 ions/cm2. After then, the photoresist pattern 26 is removed using an ashing process.
Subsequently, as shown in FIG. 1e, a photoresist pattern 30 is formed on the substrate 10, using a photolithography process, to expose the high-voltage MOS transistor region B. Using a LDD implantation process, conductive impurities are implanted in the substrate 10 exposed by the gate electrode 24 of the high-voltage MOS transistor region B to form a second LDD region 32. For example, in the second LDD implantation for a NMOS transistor, As ions as a second conductivity type of impurity are implanted under conditions comprising an implantation energy of 50 KeV and a dose of about 1E13 ions/cm2, and continuously P ions as a second conductivity type of impurity are implanted under conditions comprising an implantation energy of 40 KeV and a dose of 2E13 ions/cm2. Similarly, in the second LDD implantation for a PMOS transistor, B or BF2 ions as a first conductivity type of impurity are implanted under conditions comprising an implantation energy of 5 KeV and a dose of 1.5E14 ions/cm2. After then, the photoresist pattern 30 is removed using an ashing process.
Next, a silicon nitride layer (not shown), as an insulating layer, is thinly formed on the entire surface of the resultant structure, and then it is etched back to form spacers at the sides of the gate electrodes 24. In addition, an implantation process is performed on the low-voltage MOS transistor region A and the high-voltage MOS transistor region B, respectively, thus forming source/drain regions for a low-voltage MOS transistor and a high-voltage MOS transistor.
However, the above-described conventional method needs a number of masks for photoresist patterns in use of forming wells, LDD regions, and source/drain regions, which results in loss of productivity and increase of production costs.